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HMC703LP4E
v02.0813
8 GHz fractional syntHesizer
For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824
978-250-3343 978-250-3373 fax Order On-line at www.hittite.com
Application Support: pll@hittite.com
serial Port open Mode Details
open Mode - serial Port Write operation
table 11. sPi open Mode - Write timing characteristics
Parameter
Conditions
Min.
Typ.
Max.
Units
t1
t2
t3
t4
t5
t6
sDI setup time
sDI hold time
sEN low duration
sEN high duration
sCK 32 Rising Edge to sEN Rising Edge
serial port Clock speed
sEN to sCK Recovery Time
3
10
DC
10
50
ns
MHz
ns
A typical WRITE cycle is shown in Figure 43.
a. The Master (host) places 24 bit data, d23:d0, MsB first, on sDI on the first 24 falling edges of sCK.
b. the slave (synthesizer) shifts in data on sDI on the first 24 rising edges of sCK
c. Master places 5 bit register address to be written to, r4:r0, MsB first, on the next 5 falling edges of
sCK (25-29)
d. slave shifts the register bits on the next 5 rising edges of sCK (25-29).
e. Master places 3 bit chip address, a2:a0, MsB first, on the next 3 falling edges of sCK (30-32). The
HMC703LP4E chip address is fixed at 000.
f.
slave shifts the chip address bits on the next 3 rising edges of sCK (30-32).
g. Master asserts sEN after the 32nd rising edge of sCK.
h. slave registers the sDI data on the rising edge of sEN.
Figure 43. Open Mode - Serial Port Timing Diagram - WRITE
open Mode - serial Port reaD operation
A typical READ cycle is shown in Figure 44.
In general, in Open Mode the LD_sDO line is always active during the WRITE cycle. During any Open Mode sPI cycle
LD_sDO will contain the data from the address pointed to by Reg 00h[4:0]. If Reg 00h[4:0] is not changed then the same
data will always be present on LD_sDO when an Open Mode cycle is in progress. If it is desired to READ from a spe-
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